Timing, signal integrity, testability, power and manufacturability, the extraordinary levels of integration afforded by very deep sub-micron (VDSM) processes amplify the
challenges of physical design. How to get your SoC chips into volume production on a fast, predictable schedule? QualChip offers professional RTL-to-GDSII design services mainly at 130-28nm and below process nodes. The central of our back-end services are our “capability” teams with their specialized design and methodology expertise and their focus on productivity. Our technology experts can become an extension of your design team and help you achieve an optimized physical implementation in the fastest
possible timeframe.
Qualchip back-end service provides:
- Design for Test
- RTL-to-gate level netlist Synthesis
- Hierarchical budgeting and design planning
- Timing and SI-aware place & route
- Full-chip timing/SI closure, static timing analysis and sign-off
- Qualifying libraries, existing netlist and design constraints
- Clock tree generation and optimization
- Power planning and optimization
- Full-chip extraction
- Full-chip physical verification
- Formal verification
- Chip finishing to tapeout
Low-Power Implementation
Leakage Power Reduction
Power Shut Off (PSO): Coarse grain power gating insertion and spice level rush current analysis;
Solation cell insertion and verification;
State retention register replacement.
Multi-VT: multi-VT libraries optimization maximizes low leakage cells replacement.
Dynamic Power Reduction
Low-Power CTS: Optimized clock gating insertion;
Minimized clock tree depth and optimization transition control.
Multiple Supply Voltage(MSV): Level-shifter insertion between power islands.
Dynamic Voltage Frequency Scaling (DVFS): Accurate power mode verification;
Dynamic clock tree balancing;
Cross-domain logic synchronization.
For more information, please send mail to: business@qualchiptech.com
